The present invention relates to semiconductor memory cells and methods of fabricating the same and, more particularly, to magnetic random access memory cells and methods of fabricating the same.
Magnetic random access memory (MRAM) devices have been widely used as non-volatile memory devices, which can be operated at a low voltage and/or a high speed. In a unit cell of the MRAM devices, one bit of data is stored in a magnetic tunnel junction (MTJ) of a magnetic resistor. The MTJ generally includes first and second ferromagnetic layers and a tunneling insulation layer interposed between the first and second ferromagnetic layers. Magnetic polarization of the first ferromagnetic layer, which is also referred to as a free layer, can be changed by a magnetic field that crosses the MTJ. The magnetic field can be induced by a current that flows around the MTJ. The magnetic polarization of the free layer may be parallel or anti-parallel to the magnetic polarization of the second ferromagnetic layer, also referred to as a pinned layer. Current for generating the magnetic field flows through a conductive layer, which is referred to as a digit line, disposed around the MTJ.
According to spintronics based on quantum mechanics, in the event that magnetic spins in the free layer and the pinned layer are arrayed to be parallel with each other, a tunneling current flowing through the MTJ exhibits a maximum value. On the other hand, in the event that the magnetic spins in the free layer and the pinned layer are arrayed to be anti-parallel with each other, the tunneling current flowing through the MTJ has a minimum value. Thus, data of the MRAM cell may be determined according to the direction of the magnetic spins in the free layer.
FIG. 1 is a cross-sectional view illustrating a conventional MRAM cell. Referring to FIG. 1, a first interlayer insulating layer 3 is stacked on a semiconductor substrate 1. A digit line 5 is disposed on the first interlayer insulating layer 3. The digit line 5 and the first interlayer insulating layer 3 are covered with a second interlayer insulating layer 7. A magnetic resistor 16 is disposed on the second interlayer insulating layer 7 to overlap with a predetermined region of the digit line 5. he magnetic resistor 16 includes a lower electrode 11, a MTJ 13 and an upper electrode 15 which are sequentially stacked. The magnetic resistor 16 and the second interlayer insulating layer 7 are covered with a third interlayer insulating layer 17. A bit line 19, electrically connected to the upper electrode 15, is disposed on the third interlayer insulating layer 17.
The lower electrode 11 may be electrically connected to a predetermined region of the semiconductor substrate 1. Therefore, the lower electrode 11 may be formed to have a wider width than the digit line 5. That is to say, the lower electrode 11 may be formed to have an extension A that does not overlap with the digit line 5. The extension A is electrically connected to a predetermined region of the semiconductor substrate 1 through a lower electrode plug 9 that penetrates the first and second interlayer insulating layers 3 and 7.
As a result, the extension A of the lower electrode 11 makes it difficult to shrink the conventional MRAM cell shown in FIG. 1.
In recent years, an MRAM cell having split sub-digit lines has been proposed to solve the above-mentioned problems. In addition, a cladding layer surrounding a sidewall and a bottom surface of the digit lines is widely used so as to enhance a writing efficiency of the MRAM cell. An MRAM cell employing a cladding layer is discussed in U.S. Pat. No. 6,430,084 B1 to Rizzo et al., entitled “Magnetic Random Access Memory having Digit Lines and Bit Lines with a Ferromagnetic Cladding Layer.”
FIG. 2 is a cross-sectional view illustrating an MRAM cell having the cladding layer, as disclosed in U.S. Pat. No. 6,430,084 B1, that surrounds the split sub-digit lines.
Referring to FIG. 2, a first interlayer insulating layer 23 is provided on a semiconductor substrate 21. First and second parallel split sub-digit lines 27a and 27b are disposed in the first interlayer insulating layer 23. Both sidewalls and a bottom surface of the first sub-digit line 27a are surrounded by a first cladding layer 25a, and both sidewalls and a bottom surface of the second sub-digit line 27b are also surrounded by a second cladding layer 25b. A second interlayer insulating layer 29 is provided on the semiconductor substrate having the first and second sub-digit lines 27a and 27b as well as the first and second cladding layers 25a and 25b. A predetermined region of the semiconductor substrate 21 is electrically connected to an MTJ contact plug 31 that penetrates the first and second interlayer insulating layers 23 and 29. The MTJ contact plug 31 passes through a region between the first and second sub-digit lines 27a and 27b. An MTJ 33 is disposed on the second interlayer insulating layer 29 to come into contact with the MTJ contact plug 31.
When a writing current is forced into the split sub-digit lines 27a and 27b in order to store a bit of data in the MRAM cell shown in FIG. 2, first and second magnetic fields 35a and 35b are generated. The first and second magnetic fields 35a and 35b are mainly distributed on one side and the other side of the MTJ 33 as shown in FIG. 2, respectively. In other words, it may be difficult to generate a magnetic field that is uniformly distributed throughout the MTJ 33 during the writing operation. This is because all sidewalls of the first and second sub-digit lines 27a and 27b are surrounded by the first and second cladding layers 25a and 25b. Thus, there is a limitation in improving the writing efficiency of the MRAM cell, even though the MRAM cell having the split sub-digit lines 27a and 27b employs the cladding layers that concentrate the magnetic fields.